Flash memory devices have recently been through a rapid development. The flash memory devices are able to retain the stored data for a very long period of time without applying a voltage. Further, the reading rate of the flash memory devices is relatively high; and it is easy to erase stored data and rewrite data into the flash memory devices. Thus, the flash memory devices have been widely used in micro-computers, and automatic control systems, etc. To increase the bit density and reduce the bit cost of the flash memory devices, three-dimensional (3D) NAND (Not AND) flash memory devices have been developed.
FIG. 1 illustrates an electric circuitry diagram of a 3D NAND device. As shown in FIG. 1, the circuitry of the 3D NAND device includes bit lines (BLs), upper selecting gates (Upper SGs), control gates (CGs), lower selecting gates (lower SGs), and source lines (SLs), etc. The SLs maintain the unidirectional current output from the memory array. A certain memory may be selected from three-dimensional respectively using the selecting signal of the BLs, the common selecting signal of the upper SGs and the lower SGs, and the selecting signal of the CGs. The selecting signal of the CGs may control the selecting of a certain lateral layer of memory.
FIG. 2 illustrates the structure of a 3D NAND device. As shown in FIG. 2, the 3D NAND device includes a plurality of layers of memory structures (or memory array) 36; and a lower selecting gate LS disposed under the memory structures 36. Further, the 3D NAND device also includes an upper selecting gate US disposed right on the top of the memory structures 36; and bit lines BLs disposed over the upper selecting gate US. Further, the 3D NAND device also include a control gate CG (101) protruding from each layer of the plurality of layers of memory structures 36. Each layer of memory structures 36 are electrically connected with the control-voltage-signal-input-lines 29 through the contact vias 207 extending from the control gate CG (101).
The source region and the drain region of the memory transistor in the memory array are formed by layer-doped regions in polysilicon pillars. The memory gates are the oxide-nitride-oxide (ONO) layers surrounding the polysilicon (poly-Si) pillars. Specifically, a memory transistor includes a poly-Si body, charge trap layers and a poly-Si gate.
The control gate CG (101) of each layer of memory structure 36 may protrude from the memory structure 36; and may be electrically connected to the control-voltage-signal-input-lines 29 through metal vias 107. The control-voltage-signal-input-lines 29 may be configured as bit lines. The control gate CG (101) layers are stacked with a staircase shape from the bottom to the top. The metal vias 107 are a staggered aligned along the staircase to connect with the different bit lines (the control-voltage-signal-input-lines 29).
However, during the fabrication of the 3D NAND device, it may have etching damages to certain structures of the 3D NAND device. The etching damages may adversely affect the performance of the 3D NAND device. For example, the contact between the metal via and the control gate may not match the designed requirement, etc. Thus, the performance of the 3D NAND device may need further improvements. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.